Emergency Meeting: Image Processing Seminar

アポロ精工 アポロ精工 新横浜オフィス(旧ケーアイテクノロジー/旧市川ソフトラボラトリー)
While we mentioned that it would be held once a year, due to the number of people on the waiting list exceeding a few, it has been decided to hold an additional session at the request of the organizers. As of this announcement, we have already received applications from 15 participants. The content will broadly introduce the flow of "algorithm development, software development, and hardware development" related to image processing. Participants will approach solutions that have not been realized so far (algorithm development), learn conventional image processing methods, and practice on individual PCs to explore what can be achieved through their combinations. Among those conventional methods, we will discuss the merits and demerits of hardening one specific circuit. We will introduce trade-offs and present an example of hardening by converting a certain circuit into an FPGA. Japan Techno Center http://www.j-techno.co.jp/seminar/ID51FNVEH91/ Image Processing Algorithms, Hardware Implementation, and FPGA Selection When applying to the organizers, it has been agreed that a "Instructor Introduction Discount (10% off)" will be applied. We encourage you to consider this.

-
Date and time Thursday, Mar 19, 2015
- Capital Japan Tech Center, Seminar Room
- Entry fee Charge