Notice of Image Processing Seminar

アポロ精工 アポロ精工 新横浜オフィス(旧ケーアイテクノロジー/旧市川ソフトラボラトリー)
On November 8, 2019, we will hold a seminar titled "Fundamentals of Image Processing and Algorithms for SoCFPGA, Implementation on FPGA, and Key Points." In the first half of the seminar, we will learn about the latest information in applied industrial fields related to image processing, as well as fundamental processing techniques. We will provide a simple explanation of principles and effects for processes such as binarization, spatial filtering, labeling, feature extraction, offset, gain, shading, gamma correction, and pattern matching. To allow participants to experience the effects of these processes, we will use study and experimentation software (IP Kit 3), and each participant will operate it on their own PC (a trial version of IP Kit 3 can be taken home). In the second half, we will learn about the separation of hardware and software and practice selecting implementation methods. Furthermore, we will clarify the requirements for the parts that have been decided to be hardware-implemented, and select an FPGA considering comparisons of device manufacturers and device scale (gate scale, number of IO pins). We will explain practical examples of high-speed processing achieved through hardware implementation of the "spatial filter" learned in the first half. If you are considering attending, please contact us as there is also a "Instructor Introduction Discount System."

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Date and time Friday, Nov 08, 2019
10:30 AM ~ 05:30 PM
- Capital [Tokyo] Japan Techno Center Training Room 〒 163-0722 2-7-1 Nishi-Shinjuku, Shinjuku-ku, Tokyo Odakyu Dai-Ichi Seimei Building (22nd floor) - 10 minutes on foot from JR "Shinjuku Station" West Exit - 8 minutes on foot from Tokyo Metro Marunouchi Line "Nishi-Shinjuku Station" - 5 minutes on foot from Toei Oedo Line "Tocho-Mae Station" Phone number: 03-5322-5888 FAX: 03-5322-5666
- Entry fee Charge Instructor introduction discount available.