Notice of the Image Processing Seminar

アポロ精工 アポロ精工 新横浜オフィス(旧ケーアイテクノロジー/旧市川ソフトラボラトリー)
On October 15, 2020, we will hold a seminar titled "Fundamentals of Image Processing and Algorithms for SoCFPGA, Implementation on FPGA and Key Points." In the first half of the seminar, we will learn about the latest information in the application industries related to image processing, as well as fundamental processing techniques. We will provide a simple explanation of principles and effects for processes such as binarization, spatial filtering, labeling, feature extraction, offset, gain, shading, gamma correction, and pattern matching. To experience the effects of these processes, participants will use study and experimental software to operate on their own PCs (the software can be taken home). In the second half, while learning about the separation of hardware and software, we will practice selecting implementation methods. Furthermore, we will clarify the requirements specifications for the parts that have been decided to be hardened, and select FPGA considering comparisons of device manufacturers and device scale (gate scale, number of IO pins). We will explain a practical example of high-speed processing through the hardening of the "spatial filter" learned in the first half. Finally, we will conduct an image processing demonstration tailored to the participants' requests. For those considering attending, we also have a "Instructor Introduction Discount System." Please contact us.

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Date and time Thursday, Oct 15, 2020
10:30 AM ~ 05:30 PM
- Capital [Tokyo] Japan Techno Center Training Room 〒 163-0722 2-7-1 Nishi-Shinjuku, Shinjuku-ku, Tokyo Odakyu Dai-ichi Seimei Building (22nd floor) - 10 minutes on foot from JR "Shinjuku Station" West Exit - 8 minutes on foot from Tokyo Metro Marunouchi Line "Nishi-Shinjuku Station" - 5 minutes on foot from Toei Oedo Line "Tocho-mae Station" Phone number: 03-5322-5888 FAX: 03-5322-5666
- Entry fee Charge Instructor introduction discount available.