Large-scale FPGA
アポロ精工 アポロ精工 新横浜オフィス（旧ケーアイテクノロジー/旧市川ソフトラボラトリー）
It seems that the era of expressing the scale of FPGAs in terms of ASIC gate equivalents is over. A unit is defined as one logic cell, which consists of a logic circuit (actually a LUT) and a flip-flop (FF), and the number of these blocks is one indicator of scale. Even so, since we are talking about millions of cells, it is rare for the desired circuit not to fit, excluding component costs. Circuits that traditionally consumed logic cells, such as multipliers, have dedicated DSP blocks available. The embedded memory, which is a strength of FPGAs, is also in the Mb class. Thus, SoC FPGAs, which incorporate CPUs (currently both top manufacturers use ARM) alongside logic circuits on the same silicon, are being developed. From the perspective of a development engineer, while CPUs offer many advantages, it is important to remember that they reduce the number of I/O pins. Other hardware accelerators that have been announced recently seem to circle back to ASSPs (Application-Specific Standard Products) when examined closely, but I am very interested and look forward to the day when I can get my hands on actual devices. *News is distributed through our company's newsletter.
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