[Image Processing Engineer Column] Development Environment for Software and Hardware
アポロ精工 アポロ精工 新横浜オフィス（旧ケーアイテクノロジー/旧市川ソフトラボラトリー）
Those who work in FPGA circuit design are likely troubled by the "logic synthesis time" of various tools from different companies. This theme has persisted since the era when the concept of FPGA first emerged. It was not an issue during the PAL and GAL era, but it was a consideration in contemporary ASIC design. While the performance of CPUs in personal computers has dramatically improved, the logic synthesis time for FPGAs still takes an excessive amount of time. In a simulation environment, we create a "test bench," but using features that allow us to view the internal signal states during debugging on the actual chip (such as chip scopes or signal taps) further extends the logic synthesis time. This topic is often difficult for software engineers to understand. Fortunately, our company operates with a small team, and since hardware, firmware, and device driver personnel work closely together, we understand the time it takes to respond to requests like "please check this signal" from the firmware team. This time, I introduced an example where the evolution of development environment performance has not kept pace. *News is distributed through our company newsletter.
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