IP core "AndesCore AX25"
64-bit CPU architecture! It can access an address space significantly exceeding 4GB.
The "AndesCore AX25" is a compact 64-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It is optimized for high-performance embedded applications that require access to an address space exceeding 4GB. Options such as branch prediction for efficient branch instruction execution, instruction and data caches, local memory for low-latency access, and ECC for L1 memory soft error protection are available. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ DSP/SIMD ISA suitable for digital signal processing ■ Floating-point extension ■ Andes extensions that enable high performance and high functionality *For more details, please refer to the related links or feel free to contact us.
basic information
【Other Specifications (Partial)】 ■ Andes Custom Extension (ACE) available for customization and proprietary instructions ■ Access to a 64-bit CPU architecture with an address space significantly exceeding 4GB ■ High code density with a mixed instruction format of 16/32 bits ■ Branch prediction to accelerate control codes ■ Return Address Stack (RAS) to speed up procedure returns ■ Memory Management Unit (MMU) and Physical Memory Protection (PMP) *For more details, please refer to the related links or feel free to contact us.
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For more details, please refer to the related links or feel free to contact us.
