IP core "AndesCore A25"
It also includes modes for low power consumption and power management, as well as a debugging interface!
The "AndesCore A25" is a 32-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It achieves high performance per MHz and operates at high frequencies with a low gate count. Additionally, the Andes Custom Extension (ACE) is offered as an option to add custom instructions that lead to performance improvements and optimization of performance/power. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ DSP/SIMD ISA suitable for digital signal processing ■ Floating-point extension ■ Andes extension features that enable high performance and high functionality *For more details, please refer to the related links or feel free to contact us.
basic information
【Other Specifications (Partial)】 ■ Andes Custom Extension (ACE) available for customization and proprietary instructions with a separate license ■ 32-bit, 5-stage CPU architecture ■ High code density with mixed 16/32-bit instruction format ■ Branch prediction to accelerate control codes ■ Return Address Stack (RAS) to speed up procedure returns ■ Memory Management Unit (MMU) and Physical Memory Protection (PMP) *For more details, please refer to the related links or feel free to contact us.
Price range
Delivery Time
Applications/Examples of results
For more details, please refer to the related links or feel free to contact us.
