IP core "AndesCore D25F"
A flexibly configurable platform to support a wide range of system event scenarios!
The "AndesCore D25F" is a 32-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. For Linux-based applications, it supports the RISC-V P-extension (draft) DSP/SIMD ISA, which has been significantly contributed to by Andes Technology, as well as single-precision/double-precision floating-point instructions and an MMU. Additionally, options are available for branch prediction for efficient branch instruction execution, instruction and data caches, local memory for low-latency access, and ECC for L1 memory soft error protection. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ DSP/SIMD ISA suitable for digital signal processing ■ Floating-point extension ■ Andes extensions that enable high performance and high functionality *For more details, please refer to the related links or feel free to contact us.
basic information
【Other Specifications (Partial)】 ■ 32-bit, 5-stage CPU architecture ■ High code density mixed 16/32-bit instruction format ■ Branch prediction to accelerate control codes ■ Return Address Stack (RAS) to speed up procedure returns ■ Memory Management Unit (MMU) and Physical Memory Protection (PMP) *For more details, please refer to the related links or feel free to contact us.
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