IP core "AndesCore N25F"
High code density 16/32-bit mixed instruction format!
The "AndesCore N25F" is a 32-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It achieves high performance per MHz and operates at high frequencies with a low gate count, supporting single-precision and double-precision floating-point instructions. Additionally, the Andes Custom Extension (ACE) is offered as an option to add custom instructions that lead to performance improvements and optimization of performance/power. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ Floating-point extension ■ Andes extensions capable of achieving high performance and high functionality ■ Andes Custom Extension (ACE) available for separate licensing for customization and custom instructions *For more details, please refer to the related links or feel free to contact us.
basic information
【Other Specifications (Partial)】 ■ 32-bit, 5-stage CPU architecture ■ High code density mixed 16/32-bit instruction format ■ Branch prediction to accelerate control codes ■ Return Address Stack (RAS) to speed up procedure returns ■ Physical Memory Protection (PMP) ■ Enhanced vectorized interrupt handling for real-time performance ■ Advanced CoDense technology that contributes to reducing program code size *For more details, please refer to the related links or feel free to contact us.
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