IP core "AndesCore N22"
There are configurable settings that allow for trade-offs between core size and performance requirements!
The "AndesCore N22" is a 32-bit, dual-stage pipeline CPU IP core based on the AndeStar V5 architecture, designed for embedded applications that require low power consumption and small circuit size. It complies with RISC-V technology and features several efficient performance capabilities, including simple dynamic branch prediction, instruction cache, and local memory. Additionally, it comes with a rich set of optional features such as a JTAG debug interface for development support. 【Specifications (partial)】 ■ AndeStar V5/V5e Instruction Set Architecture (ISA) based on RISC-V technology ■ Supports RV32IMAC/EMAC ■ Andes extensions that enable high performance and high functionality ■ 32-bit, dual-stage pipeline CPU architecture ■ High code density with mixed 16/32-bit instruction formats *For more details, please refer to the related links or feel free to contact us.
basic information
【Other Specifications (Partial)】 ■ Branch prediction to accelerate control codes ■ Configurable multipliers ■ Physical Memory Protection (PMP) ■ Core-local Interrupt Controller (CLIC) with configurable assignment and priority for vectors ■ StackSafe hardware to assist in measuring stack size and detecting runtime overflows/underflows ■ Configurable settings to trade off between core size and performance requirements *For more details, please refer to the related links or feel free to contact us.
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For more details, please refer to the related links or feel free to contact us.
