IP core "AndesCore AX25MP"
64-bit CPU architecture! It can access an address space significantly exceeding 4GB.
The "AndesCore AX25MP" is a 64-bit multi-core CPU IP core based on the AndeStar V5 architecture. It features an MMU for Linux-based applications, branch prediction for efficient branch instruction execution, level-1 instruction and data caches, and local memory for low-latency access. Additionally, it supports up to 4 cores and a level-2 cache controller with instruction and data prefetch. 【Specifications (partial)】 ■ Symmetric multiprocessor with up to 4 cores ■ Supports level-2 cache and cache coherence ■ AndeStar V5 Instruction Set Architecture (ISA) Compliant with RISC-V ISA IMACFDN, including Andes performance/function extensions ■ Floating-point extension *For more details, please refer to the related links or feel free to contact us.
basic information
【Other Specifications (Partial)】 ■ DSP/SIMD ISA suitable for digital signal processing * Customization and unique instructions available through a separate license with Andes Custom Extension (ACE) ■ 64-bit CPU architecture, capable of accessing an address space significantly exceeding 4GB ■ High code density with a mixed instruction format of 16/32-bit ■ Branch prediction to accelerate control codes ■ Return Address Stack (RAS) to speed up procedure returns ■ Memory Management Unit (MMU) and Physical Memory Protection (PMP) * For more details, please refer to the related links or feel free to contact us.
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