IP core "AndesCore A25MP"
Symmetric multi-processor with up to 4 cores! Supports level-2 cache and cache coherence.
The "AndesCore A25MP" is a 32-bit multi-core CPU IP core based on the AndeStar V5 architecture. It features an MMU for Linux-based applications, branch prediction for efficient branch instruction execution, level-1 instruction and data caches, and local memory for low-latency access. Additionally, it supports up to four cores and a level-2 cache controller with instruction and data prefetch. 【Specifications (partial)】 ■ Symmetric multiprocessor with up to 4 cores ■ Supports level-2 cache and cache coherence ■ AndeStar V5 Instruction Set Architecture (ISA) Compliant with RISC-V ISA IMACFDN, including Andes performance/function extensions ■ Floating-point extension *For more details, please refer to the related links or feel free to contact us.
basic information
【Other Specifications (Partial)】 ■ DSP/SIMD ISA suitable for digital signal processing ■ Andes Custom Extension (ACE) available for customization and unique instructions with a separate license ■ 32-bit, 5-stage CPU architecture ■ High code density with mixed 16/32-bit instruction format ■ Branch prediction to accelerate control codes ■ Return Address Stack (RAS) to speed up procedure returns * For more details, please refer to the related links or feel free to contact us.
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