SAS Initiator IP Core for FPGA/ASIC
OOB sequence and speed negotiation sequence support!
The "IP Core SAS Initiator for FPGA/ASIC" complies with the SAS 3.0 standard and supports a maximum transfer rate of 12Gbps (1200MB/s) for Serial-SCSI (SAS) initiators (hosts). It consists of four blocks (Phy layer, LINK layer, PORT layer, TRN layer), along with a processor, SerDes, and memory interface. It is designed to connect to SAS-compliant device applications to transmit and receive OOB signals, primitives, and SAS frames. 【Specifications (Excerpt)】 ■ Compliant with SAS 3.0 standard ■ Supports SAS 3.0Gbps, 6.0Gbps, and 12.0Gbps ■ Register access to link layer/transport layer ■ Supports SerDes, PIPE, and SAPIS interfaces ■ Supports OOB sequence and speed negotiation sequence *For more details, please download the PDF or feel free to contact us.
basic information
【Other Specifications】 ■ Automatic Connection Open/Close Function ■ Automatic Credit Control Function ■ Automatic ACK/NAK Response Function *For more details, please download the PDF or feel free to contact us.
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SAS Initiator・IntelliProp
Applications/Examples of results
【Purpose】 ■ High-speed read and write access to high-performance SAS device equipment is required for SAS host applications. * For more details, please download the PDF or feel free to contact us.
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