SAS Target IP Core for FPGA and ASIC
Supports SAS 3.0Gbps, 6.0Gbps, and 12.0Gbps! Equipped with automatic credit control function.
The "IP Core SAS Target for FPGA and ASIC" complies with the SAS 3.0 standard and supports a maximum transfer rate of 12Gbps (1200MB/s) for Serial-SCSI (SAS) target (device). It consists of four blocks (Phy layer, LINK layer, PORT layer, TRN layer) and interfaces with processors, SerDes, and memory. It is designed to connect to SAS-compliant host applications to transmit and receive OOB signals, primitives, and SAS frames. 【Specifications (Excerpt)】 ■ Compliant with SAS 3.0 standard ■ Supports SAS 3.0Gbps, 6.0Gbps, and 12.0Gbps ■ Register access to link layer/transport layer ■ Supports SerDes, PIPE, and SAPIS interfaces ■ Supports OOB sequence and speed negotiation sequence *For more details, please download the PDF or feel free to contact us.
basic information
【Other Specifications】 ■ Automatic Connection Open/Close Function ■ Automatic Credit Control Function ■ Automatic ACK/NAK Response Function *For more details, please download the PDF or feel free to contact us.
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Model number/Brand name
SAS Target・IntelliProp
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Fujisoft has a history of 40 years in embedded development since its founding, accumulating various experiences in both software and hardware. Based on the experience cultivated over many years, a team of over 2,000 embedded technology experts provides embedded services across a wide range of fields, including automotive, medical, industrial, and home appliances. Our seamless development system, covering everything from hardware to software, allows our consultants to propose solutions starting from the "soft phase," such as requirements specification, and we offer a consistent solution that encompasses development, research, testing, and production.