[Book] Reducing CTE in Semiconductor Packaging and Warpage Countermeasures (No. 2367)
[Available for preview] ~ Chiplets, responding to 2.5D/3D high-density packaging ~
◎What are the key points for integrating materials with different thermal expansion coefficients and elastic moduli? ◎A comprehensive overview of thermal stress countermeasures required in high thermal density environments and composite packaging. －－－－－－－－－－－－－－－－－－－－－ ■Key Points of This Book ◆Design for reduced warping and low thermal expansion of materials ◆Surface treatment and dispersion technology for fillers ◆Reduction of thermal stress using negative thermal expansion materials ◆Evaluation and simulation techniques
basic information
■Table of Contents Chapter 1: Development Trends of Element Technologies for Miniaturization and Integration of Semiconductor Packages Chapter 2: Development Trends of Filler Materials Enabling Improved Thermal Conductivity and Low Thermal Expansion Chapter 3: Development Trends of Negative Thermal Expansion Materials Chapter 4: Surface Treatment, Dispersion, and Filling Techniques for Fillers Chapter 5: Development Trends of Low Thermal Expansion Substrate Materials and Glass Substrates Chapter 6: Development of Semiconductor Encapsulation Materials and Stress Reduction Chapter 7: Development of Joining Materials Chapter 8: Development Trends of Low CTE Resin Materials Chapter 9: Evaluation and Simulation Technologies in Semiconductor Package Materials －－－－－－－－－－－－－－－－－－－－－ ●Publication Date: July 31, 2026 ●Format: A4, 395 pages ●Authors: 33 individuals ●ISBN: 978-4-86798-163-4 －－－－－－－－－－－－－－－－－－－－－
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88,000 yen (including tax) [Shipping included] Various discount programs are available. Please contact us.
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P2
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P2
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2367 Semiconductor package warpage
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