DapTechnology's FireGate PHY Layer Core

FireGate is an IP core that complies with IEEE-1394b and supports all AS5643 requirements.

Advantages of implementing a complete 1394 I/O interface using FPGA Standalone solution: By combining PHY IP with link layer IP, it is possible to create smaller products. Additional components can be added to create a system-on-chip (SoC) solution. Flexible number of ports: Commercially available PHY chips have a fixed number of ports, which is often excessive for small peripherals. On the other hand, host adapters are likely to benefit from three or more ports, and hubs can have even more ports. In the case of PHY based on FPGA technology, users can customize the number of ports as needed. Optional debugging and testing features: Optionally, debugging and testing features such as BERT (Bit Error Rate Testing) can be included. Field upgradable: The FPGA used is field-upgradable, allowing new features and bug fixes to be added even when the device is already in the field. Cost-effective ASICs: Once the design is complete, the IP solution provides a very cost-effective way to spin custom ASICs.

basic information

■Main Features - A complete IP solution supporting IEEE-1394b-2008 and AS5643 - Support for speeds from S100 to S3200 - Single speed support (S100, S200, S400, ...) - Multi-speed support (S100-S400, S800-S3200) - Scalable PHY port count from 1 to 16 - Integrated support for AS5643 (Mil1394) extension ■Supported FPGAs The FireGate IP core supports various FPGA families. Currently, the following platforms are supported, but please feel free to contact us for the latest information. - Xilinx (Spartan, Artix, Kintex, Virtex, Zynq, etc.) - Altera (Cyclone) - MicroSemi (IGLOO2, SmartFusion2)