Report: Oracle SPARC T5 Multi-Core Processor
This is a structural analysis report created using TSMC's 28nm HP process.
The "Oracle SPARC T5 Multi-Core Processor" is a structural analysis report created using TSMC's 28nm HP process. The T5 operates at a clock speed of 3.6GHz and is a 16-core SoC. It is built using TSMC's 28nm HP CMOS process with 13 metal layers (12 Cu, 1 Al) and high-K metal gate (HKMG), featuring 16KB of L1 data cache, 16KB of L1 instruction cache, and 128KB of L2 cache for each core, along with an additional 8MB of shared L3 cache. **Features** - Two PCI-Express 3.0 controllers integrated into the die - Four DDR3 memory controllers included - Device: <110> channel-oriented transistors For more details, please download the catalog or contact us.
basic information
【Device Features】 - NMOS/PMOS gates with a length of approximately 30nm and a contacted gate pitch of 120nm - SRAM array with a 110nm metal 1 pitch - 6T SRAM has a cell size of 0.15um. For more details, please download the catalog or contact us.
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【Purpose】 ○ As a structural analysis report *For details, please request the materials or view the PDF data from the download.*
