Core technology supporting OSRDA: FSNIP
Can be manufactured with small devices and in small area factories! Achieving an excellent method that does not cause alignment shifts.
We would like to introduce our technology, 'FSNIP (Free Substrate material Narrow pitch Imprinted Process).' By transferring conductive paste onto a substrate using the imprinting method, we can simultaneously form wiring and bumps with a pitch of 40μm or less, with a minimum pitch of 10μm. Due to the transfer wiring method, it can be manufactured with low-cost equipment and in small area factories, and because wiring and bumps are formed simultaneously, it achieves an excellent method that does not result in alignment shifts. 【Features】 ■ Transfer of conductive paste onto the substrate using the imprinting method ■ Simultaneous formation of wiring and bumps with a pitch of 40μm or less, with a minimum pitch of 10μm ■ Can be manufactured with low-cost equipment and in small area factories ■ No alignment shifts occur *For more details, please refer to the PDF document or feel free to contact us.
basic information
【Other Features】 ■ Imprint wiring and bump formation on any substrate - Minimum wiring pitch of 10μm, minimum wiring width of 5μm, maximum aspect ratio of 2 - Wiring pitch, wiring width, and aspect ratio can be freely configured *For more details, please refer to the PDF document or feel free to contact us.
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For more details, please refer to the PDF document or feel free to contact us.
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Connectec Japan Co., Ltd. is a process development-oriented semiconductor backend contract OSRDA that creates new packages through its core technologies, bump-on-material and damage-free bonding, known as MONSTER PAC. If you are facing challenges with semiconductor chip assembly or MEMS chip manufacturing and assembly, please consult us first. Our experienced development team will respond to any of your requests.