Kistler Japan G.K. Head office Official site

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Registration for the webinar on 'Visualization Solutions for Error Modes in Power Semiconductor Manufacturing and Post-Processing' is now open.

Kistler Japan G.K.

Kistler Japan G.K. Head office

The registration for this year's first webinar has started! In the post-manufacturing processes of semiconductors, such as dicing, die bonding, and wire bonding, where mechanical stress is applied to the chips, visual inspections and electrical tests after the process are essential. However, these inspection results alone make it difficult to directly understand the error modes during the process. With Kistler's piezoelectric sensors, we can measure the changes in load applied to the product during the process with high precision and dynamically. By understanding the details of error modes from changes during processing, we will introduce hints for process improvement. [Date and Time] 1st Session: January 31, 2024 (Wednesday) 15:05 - 15:50 2nd Session: February 8, 2024 (Thursday) 15:05 - 15:50 Both sessions will cover the same content, so please click on "Register for the Webinar Here" in the "Related Links" below to sign up.

Can the defect rate be improved through post-processing appearance inspection?

Related Links

Register for the webinar here
Clicking will take you to the webinar registration screen, so please be sure to register in advance and participate!
Reference Video
Visualization of error modes in the power semiconductor manufacturing process and dicing